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Use volatile sram, equipped in most embedded processors, to save the program states across power failures with its data retention feature. Data retention refers to sram’s ability to retain. The drv exhibits significant intra.
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Motivation to design a low power sram. This paper presents several techniques for leakage current reduction for sram cell. Low power design, low leakage. This paper investigates the root cause of data.
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This paper provides a quantitative measure of reliability by calculating the probability distribution function (pdf) of errors induced by thermal noise in latches and srams operating in. Our probabilistic error model can handle error rate analysis for arrays of latches or full srams on time scales from seconds to years without excessive computational overhead.
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